DS1624
1 f 1
PARAMETER SYMBOL CONDITIONS
MIN
TYP MAX UNITS NOTES
Fall Time of Both
SDA and
SCL Signals
t
F
Fast mode
20+0.1C
B
300
ns
8, 9, 11
Standard mode
20+0.1C
B
300
Setup Time for
STOPCondition
t
SU:STO
Fast mode
0.6
祍
11
Standard mode
4.0
Capacitive Load for
Each Bus Line
C
B
400
pF
In ut Ca acitance
C
5
F
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
DD
is switched off.
3. I
CC
specified with SDA pin open.
4. I
CC
specified with V
CC
at 5.0V and SDA, SCL = 5.0V, 0?/SPAN>C to +70?/SPAN>C.
5. EEPROM inactive, temperature sensor in shutdown mode.
6. Write occurs between 0癈 and +70癈.
7. After this period, the first clock pulse is generated.
8. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
e 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit
to the SDA line t
R(MAX)
+t
SU:DAT
= 1000+250 = 1250ns before the SCL line is released.
9. For example, if C
B
= 300pF, then t
R(MIN)
= t
F(MIN)
= 50ns.
10. A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined
region of SCLs falling edge.
11. See the timing diagram (Figure 2). All timing is referenced to 0.9V
DD
and 0.1V
DD
.
12. Limits are 100% production tested at T
A
= +25癈 and/or T
A
= +85癈. Limits over the operating
temperature range and relevant supply voltage are guaranteed by design and characterization.
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